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74HC574 Octal 3-State Noninverting D Flip-Flop
High-Performance Silicon-Gate CMOS
The 74HC574 is identical in pinout to the LS574. The device inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. Data meeting the set-up time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the states of the flip-flops but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be stored even when the outputs are not enabled. The HC574 is identical in function to the HC374A but has the flip-flop inputs on the opposite side of the package from the outputs to facilitate PC board layout.
Features http://onsemi.com MARKING DIAGRAMS
20 20 1 TSSOP-20 DT SUFFIX CASE 948E 1 HC574 A L Y W G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package HC 574 ALYW G G
* * * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 266 FETs or 66.5 Equivalent Gates This is a Pb-Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
March, 2007 - Rev. 1
1
Publication Order Number: 74HC574/D
74HC574
OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CLOCK OE L L L H
FUNCTION TABLE
Inputs Clock D H L X X Output Q H L No Change Z
L,H, X
X = Don't Care Z = High Impedance
Figure 1. Pin Assignment
D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 CLOCK OUTPUT ENABLE
2 3 4 5 6 7 8 9 11 1
19 18 17 16 15 14 13 12
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 PIN 20 = VCC PIN 10 = GND NONINVERTING OUTPUTS
Figure 2. Logic Diagram
Design Criteria Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product *Equivalent to a two-input NAND gate.
Value 66.5 1.5 5.0 0.0075
Units ea. ns mW pJ
IIIIIIIIIIIIIII IIIIIIIIIIIIIII
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74HC574
MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA PD MSL FR VESD ILatchup DC Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance Power Dissipation in Still Air at 85_C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Latchup Performance Oxygen Index: 30% - 35% Human Body Model (Note 2) Machine Model (Note 3) Above VCC and Below GND at 85_C (Note 4) TSSOP TSSOP (Note 1) Parameter Value *0.5 to )7.0 *0.5 to VCC )0.5 *0.5 to VCC )0.5 $20 $35 $35 $75 $75 *65 to )150 260 )150 128 450 Level 1 UL 94 V-0 @ 0.125 in >2000 >200 $300 V mA Unit V V V mA mA mA mA mA _C _C _C _C/W mW
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to EIA/JESD78. 5. For high frequency or heavy load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI, VO TA tr, tf DC Supply Voltage DC Input Voltage, Output Voltage Operating Temperature, All Package Types Input Rise and Fall Time (Figure 3) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Parameter (Referenced to GND) (Referenced to GND) Min 2.0 0 *55 0 0 0 Max 6.0 VCC )125 1000 500 400 Unit V V _C ns
6. Unused inputs may not be left open. All inputs must be tied to a high- or low-logic input voltage level.
ORDERING INFORMATION
Device 74HC574DTR2G Package TSSOP-20* Shipping 2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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74HC574
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions Vout = VCC - 0.1 V |Iout| v 20 mA VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 2.0 4.5 6.0 |Iout| v 2.4 mA |Iout| v 6.0 mA |Iout| v 7.8 mA 3.0 4.5 6.0 6.0 6.0 Guaranteed Limit *55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 $0.1 $0.5 v85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 $1.0 $5.0 v125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.8 1.9 4.4 5.9 2.2 3.7 5.2 0.1 0.1 0.1 0.4 0.4 0.4 $1.0 $10 mA mA Unit V
VIL
Maximum Low-Level Input Voltage
Vout = 0.1 V |Iout| v 20 mA
V
VOH
Minimum High-Level Output Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage
Vin = VIH |Iout| v 20 mA Vin = VIH
V
VOH
V
VOL
Vin = VIL |Iout| v 20 mA Vin = VIL
V
Iin IOZ
Maximum Input Leakage Current Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 mA
ICC
6.0
4.0
40
40
mA
7. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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74HC574
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns)
Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 3 and 6) VCC (V) 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 60 2.0 3.0 4.5 6.0 Guaranteed Limit *55 to 25_C 6.0 15 30 35 160 105 32 27 150 100 30 26 140 90 28 24 60 27 12 10 10 15 v85_C 4.8 10 24 28 200 145 40 34 190 125 38 33 175 120 35 30 75 32 15 13 10 15 v125_C 4.0 8.0 20 24 240 190 48 41 225 150 45 38 210 140 42 36 90 36 18 15 10 15 Unit MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q (Figures 3 and 6)
ns
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable to Q (Figures 4 and 7)
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable to Q (Figures 4 and 7)
ns
tTLH, tTHL
Maximum Output Transition Time, any Output (Figures 3 and 6)
ns
Cin Cout
Maximum Input Capacitance Maximum Three-State Output Capacitance, Output in High-Impedance State
pF pF
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Enabled Output)* 24 pF
*Used to determine the no-load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . For load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (CL = 50 pF; Input tr = tf = 6.0 ns)
Guaranteed Limit VCC Symbol tsu Parameter Minimum Setup Time, Data to Clock Figure 5 (V) 2.0 3.0 4.6 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C Min 50 40 10 9.0 5.0 5.0 5.0 5.0 75 60 15 13 1000 800 500 400 Max v 85_C Min 65 50 13 11 5.0 5.0 5.0 5.0 95 80 19 16 1000 800 500 400 Max v 125_C Min 75 60 15 13 5.0 5.0 5.0 5.0 110 90 22 19 1000 800 500 400 Max Unit ns
th
Minimum Hold Time, Clock to Data
5
ns
tw
Minimum Pulse Width, Clock
3
ns
tr, tf
Maximum Input Rise and Fall Times
3
ns
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74HC574
tr CLOCK 90% 50% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL tPHL tf
SWITCHING WAVEFORMS
VCC GND Q 3.0 V 1.3 V tPZL 1.3 V tPZH Q tPHZ 10% 90% tPLZ GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE
Figure 3.
Figure 4.
TEST POINT
VALID DATA 50% tsu CLOCK th 50%
OUTPUT VCC GND VCC GND *Includes all probe and jig capacitance. DEVICE UNDER TEST CL*
Figure 5.
Figure 6.
C Q D C Q D C Q D C Q D C Q D C Q D C Q D C Q D 11 1 19
D0
2
Q0
D1
3
18
Q1
D2 TEST POINT OUTPUT DEVICE UNDER TEST 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
4
17
Q2
D3
5
16
Q3
D4
6
15
Q4
CL*
D5 *Includes all probe and jig capacitance.
7
14
Q5
D6
8
13
Q6
Figure 7. Test Circuit
D7 9
12
Q7
CLOCK OUTPUT ENABLE
Figure 8. Expanded Logic Diagram http://onsemi.com
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74HC574
PACKAGE DIMENSIONS
TSSOP-20 CASE 948E-02 ISSUE C
20X
K REF
M
2X
L/2
20
11
J J1 B -U- N
L
PIN 1 IDENT 1 10
0.15 (0.006) T U
S
A -V-
N F DETAIL E -W-
DIM A B C D F G H J J1 K K1 L M
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
16X
16X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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IIII IIII IIII
SECTION N-N 0.25 (0.010) M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.65 PITCH
DIMENSIONS: MILLIMETERS
74HC574
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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74HC574/D

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